﻿ Arithmetic Unit

# Arithmetic Unit

A ripple adder is a circuit that uses a half adder for the sum of the least significant bits and a full adder for each additional pair of bits. It is called a ripple adder because the carry bit propagates (ripples) from right to left (from the least significant bit position to the most significant.)

### Ripple Adder with Carry In

Replacing the half-adder on the right with a full-adder (see the illustration below) gives us a couple of advantages. One is that two of these 4-bit ripple adders can be used to create an 8-bit adder where the carry out from the low-order ripple adder carries into the high-order ripple adder. Similarly, four 4-bit ripple adders can be used to create a 16-bit adder.

A second advantage is that the carry into the low-order adder can be connected to an input signal called INC. If this input is low, the adder functions as normal. If this input is high then the output of the adder is incremented by one. This is discussed in more detail in the section that follows.

One shortcoming of a ripple adder is that the output of the adder is not stable until the carry in to the least significant bit position (the INC signal) ripples all the way up to the most-significant bit position. While the delay might be acceptable for a 4-bit adder, it becomes less and less acceptable for an 8-bit, 16-bit, 32-bit, or 64-bit adder. (You might want to read about a carry-select adder or a carry-lookahead adder.)

In the timing diagram below, a worst case scenario is illustrated. We are adding A = 1010 to B= 0101 and incrementing the result. The sum A+ B is 1111 with no carry. When this result is incremented, the result is 0000 with a carry of 1. Notice that the value of each output (from right to left in the circuit diagram; bottom to top in the timing diagram) takes longer to calculate because each output must wait until all preceding outputs have been calculated.

The animated graphic below, illustrates how the signals propagate through the circuit. For each unit of time (5 ns), the gates in green have valid inputs and can generate their final output values. Gates in light red are already stable and white gates are waiting until all of their inputs are valid. In reality, of course, these gates are busily generating results but those results won't be valid until the corresponding inputs are valid. In the animation, a gate turns green when all of its inputs are guaranteed to be valid. The animation loops continuously and begins with all of the outputs unknown (?????) and ends when the outputs are all known (10000).

## Arithmetic Unit

A ripple adder is a first step in creating an arithmetic unit which is capable of performing other arithmetic operations (besides addition). With three fairly simple improvements, we can make a much more versatile circuit. The first improvement (outlined in red in the drawing below) was introduced in the previous section. This change, all by itself, allows us to calculate A+B or A+B+1 by simply setting INC to 0 or 1 respectively. It provides additional benefits in conjunction with the other two improvements discussed below.

The second improvement (outlined in red in the illustration below) allows us to find the negative of A. Notice that each bit in A runs to an XOR gate whose other input is INVA. If INVA is 0 then the output of the XOR gate is just A because A XOR 0 = A. When INVA is 1, however, the output of the XOR gate is A' because A XOR 1 = A'. Consequently, the output generated by the XOR gates is the 1's complement of A. Notice, however, that if the INC signal is also high, the carry in to the first adder is 1. Recall that adding 1 to the 1's complement of a number yields the 2's complement of the number. This modification, then, allows us to perform 2's complement subtraction in the form B - A = B + (-A).

The final modification is outlined in red below. Each bit of the B input is run through an enable gate controlled by the ENB input. When ENB is 0 then the B input is blocked. When ENB is 1, each bit of B is passed through to the corresponding full adder. Blocking B allows our arithmetic unit to output A, A', -A, or A+1.

With INC, INVA, and ENB acting as control lines for our arithmetic unit, we now have much more than just a simple adder:

 INC INVA ENB Output 0 0 0 A 0 0 1 A + B 0 1 0 A' 0 1 1 B + A' 1 0 0 A + 1 1 0 1 A + B + 1 1 1 0 -A 1 1 1 B - A

You might think that the first row of the table is a pretty useless operation. Remember, however, that the arithmetic unit is part of an arithmetic logic unit (ALU). Allowing the arithmetic unit to generate A as its output allows the ALU to copy the contents of a register to memory.

The A' in the third and fourth rows of the table represents the one's compliment of A (the bitwise NOT). The output in the fourth row (B + A') would be of little use in a 2's complement system.

There are many other improvements that can be made to our arithmetic unit. One fairly obvious improvement would be to add an enable gate to each bit of the A input and an ENA control signal. Among other things, this would provide a way to produce the constants 0 and 1:

 INC INVA ENB ENA Output 0 0 0 0 0 1 0 0 0 1

Adding a shifter would be another improvement. Shifting a binary number to the left one place, doubles its value. Shifting a binary number to the right one place divides it by 2 (yielding the integer quotient only; the remainder is lost).

Another useful feature is an overflow flag to indicate when an overflow has occurred. An overflow occurs if there is a carry into the most significant bit adder with no carry out or a carry out of the most significant adder with no carry in (i.e., carry in XOR carry out). The overflow flag has a value of 0 if there has been no overflow and a value of 1 if an overflow occurred.

The arithmetic unit below incorporates all three of these additional improvements. You can begin to see that as the design of the arithmetic unit gets more complicated, it gets harder and harder to test and verify the design.

If you have the DEEDS digital circuit simulation software you can download Ripple Adder3.pbs and play with this circuit.