Each microinstruction is a 36-bit word whose bits drive the control lines of the CPU. The basic microinstruction format is given here:
xxxxxxxxx|xxx|xxxxxxxx|xxxxxxxxx|xxx|xxxx
Next Addr|JJJ|SSFFEEII|HOTCLSPMM|WRF|B
|MAA|LR01NNNN| POPVPCDA|REE|Bus
|PMM|LA ABVC| CSP RR|IAT|
|CNZ|81 A | |TDC|
| | | |E H|
^^ ^^^^
00 AND 0000 MDR
01 OR 0001 PC
10 NOT 0010 MBR
11 ADD 0011 MBRU
0100 SP
0101 LV
0110 CPP
0111 TOS
1000 OPC
In the descriptions below, bit numbering begins at the left with the most significant bit.
This field contains the address of the next microinstruction. It is copied to the MPC register during the execution of the current microinstruction. The value in the MPC may be altered by the jump control bits described next.
The jump control bits control branching within the microprogram.
JMPC (bit 10)
If this bit is set, the current value of the MBR register is bit-wise ORed with the 8 low-order bits of the MPC (which came from the next address field described above). Often, the next address field is set to zero when JMPC is set to one. In that case, the value in the MBR register is the address of the next microinstruction. For example, when executing a machine language program, the opcode of an instruction is the address of the block of code within the microprogram that executes that instruction. The microprogram performs a JMPC to this address when the opcode is loaded into the MBR.
JAMN (bit 11)
If this bit is set, the value of the N register is ORed with the high order bit of the MPC register. Typically, the high order bit of the value in the next address field is zero. In that case, JAMN allows a conditional jump when the value generated by the ALU is negative. If the high order bit of the next address is already one, then the value of the JAMN bit is irrelevant.
JAMZ (bit 12)
If this bit is set, the value of the Z register is ORed with the high order bit of the MPC register. Typically, the high order bit of the value in the next address field is zero. In that case, JAMZ allows a conditional jump when the value generated by the ALU is zero. If the high order bit of the next address is already one, then the value of the JAMZ bit is irrelevant.
Note: Any combination of the JMPC, JAMN, and JAMZ bits may be set at the same time.
These bits determine the operations performed by the arithmetic logic unit and the shift register.
SLL8 (bit 13)
If set, the value generated by the ALU will be shifted left 8 bits by the shifter with zero fill (a logic shift).
SRA1 (bit 14)
If set, the value generated by the ALU will be shifted right one bit with sign extension (arithmetic shift). Sign extension means that the high order bit prior to the shift will be copied into the vacated high order bit following the shift right.
Note: SLL8 and SRA1 should not both be set at the same time (it would make no sense). In the simulator, if both are set at the same time then the left logic shift will be performed first and the arithmetic right shift applied to the result.
F0, F1 (bits 15-16)
Determines the operation performed by the ALU:
00 => AND
01 => OR
10 => NOT B
11 = > ADDENA (bit 17)
If set, the A input to the ALU is enabled. Otherwise the A input is disabled; effectively setting the A input to zero.
ENB (bit 18)
If set, the B input to the ALU is enabled. Otherwise the B input is disabled; effectively setting the B input to zero.
INVA (bit 19)
If set, the value of the A input is bit-wise inverted.
Note: Clearing ENA and setting INVA has the effect of setting every bit in the A input to one which is the two's complement representation of -1.
INC (bit 20)
If this bit is set and the ALU function is ADD the output of the ALU will be A+B+1. If the ALU function is anything other than ADD then setting this bit has no effect.
These nine bits determine which register(s) receive data from the C bus during the execution of a microinstruction. Any number of these bits may be set in any given microinstruction. The bits (listed in order) correspond to the H, OPC, TOS, CPP, LV, SP, PC, MDR, and MAR registers. If a given bit is set then the corresponding register is loaded from the C-bus; otherwise it is not.
These bits control memory reads and writes.
WRITE (bit 30)
If set, the value stored in the four-byte MDR register is written to the word address stored in the MAR register. The byte address is four times the word address stored in the MAR register. The write operation is complete at the end of the next instruction.
READ (bit 31)
If set, the MDR register is loaded with the four-byte value found at the word address stored in the MAR register. The byte address is four times the word address stored in the MAR register. The read operation is complete at the end of the next instruction.
FETCH (bit 32)
If set, the MBR register is loaded with the byte value found at the address in the PC register. The fetch operation is complete at the end of the next instruction.
Note: It would make no sense to set both the WRITE and READ bits at the same time. If this is done, the simulator performs the READ operation.
Note: A fetch operation may occur simultaneously with a READ or WRITE operation. In effect, we are simulating access to cache memory in which the data and instructions are located in two separate caches.
These four bits serve as input to a 4 to 16 decoder and select which register's value is gated to the B bus:
0 => MDR
1 => PC
2 => MBR (with sign
extension)
3 => MBR (with zero fill)
4 => SP
5
=> LV
6 => CPP
7 => TOS
8 =>
OPC
9-15 =>none