There are a number of simple, fundamental circuits that can be used as
building blocks to implement larger, more complicated designs. Becoming
familiar with these building blocks and recognizing them when you see them
makes it much easier to understand a more complicated circuit diagram. We
begin with some **combinational** circuits; circuits whose
output is determined solely by its inputs. (In a **sequential** circuit, the
output is determined by the values of the inputs and the previous output.)

An enable signal is a digital signal that enables a functional unit to perform its task. Typically, if the enable signal is 1 then the unit functions normally and if the enable signal is zero then the unit is idle. In a sense, the enable signal acts as an on-off switch with regard to functionality. The circuit is not literally turned off (powered down) and turned on (powered up). More specifically, an enable signal allows a circuit's normal inputs to reach the circuit (allowing the circuit to function normally) or it blocks those inputs (preventing the circuit from doing anything useful).

Let's design a circuit with two inputs. One input, A, serves as the input to some other circuit down the line. The second input, EN, determines whether that signal is allowed through or is blocked. Here is the truth table that defines the output of this circuit:

When the enable signal is low (the top two lines), the output of this circuit is always zero regardless of the value of A. In effect the circuit is blocking the input A from reaching the output. However, when the enable signal is high (the bottom two rows, the output of this circuit is the same as the input A. In effect, it retransmits the input A. When you look at this table, you immediately recognize it as nothing more than an AND gate. What is new is the interpretation of the inputs, the output, and the task being performed.

In the circuit below, the input is a square wave. If the enable signal is low, this wave will be blocked and the output will be zero. If the enable signal is high, the square wave is unblocked and the output will be the same as the input.

The timing diagram below illustrates the behavior of this circuit. Notice that whenever the enable signal is low, the input signal is blocked. Whenever the enable signal is high, the input signal is unblocked.

Notice that his behavior is similar to a IF-THEN selection structure in computer programming. In an IF-THEN structure there are two options; perform a task or don't. In this circuit there are two options; allow the input signal to pass or don't.

A decoder has n input lines (corresponding to an n-bit binary number) and
2^{n} output lines (numbered 0 through 2^{n} - 1). Given any
bit pattern as input, the corresponding output line goes high while all
other lines go low.

The simplest possible decoder has one input (n = 1) and two
output lines (2^{n} = 2^{1} = 2) which are numbered 0 and 1.
If the input (S) is 0 then output line L0 goes high and if S is 1 then L1
goes high. The truth table is shown below along with the two output
functions.

The circuit diagram below illustrates this decoder and the timing diagram verifies its operation. Whenever the value of S is 0, L0 is selected (high) and whenever S is 1, L1 is selected.

4-Output Decoder

A 4-output decoder has two input lines (called select lines because they select the output line that goes high) and four output lines. The truth table and the four output functions are shown here:

The circuit and timing diagram are shown below. The values of the inputs AB go 00, 01, 10, 11 (corresponding to decimal 0, 1, 2, 3), and back to 00. The output line that is high goes L0, L1, L2, L3, and back to L0 accordingly.

In general, a multiplexer has n select lines and 2^{n} inputs; one of
which is allowed to pass through while the others are blocked. In effect, a
multiplexer allows one of several possible input signals to pass through the circuit.

The simplest multiplexer has 2 inputs and 1 select line that determines which input is allowed to pass through. This behavior is similar to an IF-THEN-ELSE selection structure in computer programming. In an IF-THEN-ELSE structure, some action will be performed and the purpose of the selection structure is determine which action it will be. In a 2-input multiplexer, some input will be passed through and the purpose of the circuit is to determine which one.

The truth table for a two-input multiplexer with 1 select line (S) is given below. When the select line is low, the B input values are passed through to the output. When the select line is high, the A input values are passed through. The Karnaugh map for this truth table is also shown and gives us the indicated expression for this function.

Output = S'B + SA |

An implementation of this circuit is shown here:

The timing diagram below shows how this circuit works. Input A and input B are both square wave clock signals with input B running at twice the frequency of input A. When the select line is low, input B (the higher frequency signal) is passed through to the output and when the select line is high, input A (the lower frequency signal) is passed through.

While we have designed this circuit from scratch, observe (see the illustration below) that each AND gate is just an enable circuit as discussed above and the enable signals come from a 2-output decoder.

Based on our observation above, a 4-input multiplexer can be built using a 4-output decoder with each output acting as an the enable line to an AND gate:

Consider the output from the topmost enable gate: (S1'S0')D0. Since the AND operation is associative, this can also be written as S1S0D0. That is, the two 2-input AND gates can be replaced with a single 3-input AND gate. This allows us to simplify our circuit diagram:

The timing diagram below verifies the correct operation of this circuit. The input values S1 and S0 take on the values 00, 01, 02, 03 (corresponding to decimal 0, 1, 2, 3) and then back to 00. The signals that are transmitted to the output are D0, D1, D2, and D3 respectively.

In general, an n-input multiplexer (n = 2, 4, 8, ...) is constructed from an n-output decoder with an additional input line going into each AND gate and the outputs all going into an OR gate.

A demultiplexer is the inverse of a multiplexer. It routes its single input to one of n outputs (n = 2, 4, 8, ...). Like a multiplexer, it has n select lines which determines the output to which the input is sent. In general, an n-output multiplexer (n = 2, 4, 8, ...) is constructed from an n-output decoder with the input line going into each AND gate. The input signal will be routed through the selected AND gate:

Here is the circuit for a 4-output demultiplexer:

Here is the corresponding timing diagram showing that as the values of S1 and S0 cycle through 00, 01, 10, and 11, the input signal is routed through D0, D1, D2 and D3.

A **shifter** is a circuit that can shift a binary number one
bit to the left, one bit to the right, or pass it through unchanged.
Shifting a binary number one bit to the left is the equivalent of
multiplying by 2. Shifting a binary number one bit to the right is the
equivalent of dividing by 2. In either case, the end bit (in the direction
of the shift) will be lost. Since there are 3 possible destinations for each
bit, this circuit needs two control lines which we will call SH1 and SH0:

SH1 | SH0 | Example Input | Output |

0 | 0 | 01100110 | 01100110 (no shift) |

0 | 1 | 01100110 | 01100110 (no shift) |

1 | 0 | 01100110 | 11001100 (left shift) |

1 | 1 | 01100110 | 00110011 (right shift) |

A shifter can be constructed using a 4-output demultiplexer as illustrated below. For control inputs 00 and 01, the data bit is passed straight through. For control input 10, the data bit goes to the left and for control input 11, the data bit goes to the right.

A 4-bit shifter is shown below. Notice that when you shift left there is no place for the most-significant bit to go and when you shift right there is no place for the least-significant bit to go.

In practice, using a demultiplexer as a shifter is overkill because a demultiplexer is more complicated than necessary. In the drawing below, a 1-bit shifter using a demultiplexer is shown (at the gate level) on the left and an equivalent but simpler circuit is shown on the right.

A 4-bit shifter using the simplified implementation is shown below. Notice that the circuit is simplified even further for the least-significant and most-significant bits. In a right shift, the least-significant bit is lost because there is no place to put it. Similarly, in a left shift, the least-significant bit is lost.

You should know that most arithmetic units also implement rotate right and rotate left instructions, as well. A rotate is similar to a shift except that the bit that would normally be lost is inserted at the other end. That is, in a rotate right the least-significant bit (which would lost in a shift) replaces the most-significant bit (which has shifted right). In a left shift, the most significant bit (which would be lost in a shift) replaces the least significant bit (which has shifted left).

We now consider a circuit that will allow us to add two n-bit binary numbers and generate an n-bit result and a carry.

Consider a circuit that performs 1-bit binary addition. The circuit (shown below) has 2 inputs (A and B, the bits being added) and two outputs (S and C, the sum and the carry out). In general, when you add two n-digit numbers, you must allow for a sum of n+1 digits. This is true for all bases. In this case, the carry and the sum represent the 2-digit result obtained by adding two 1-digit numbers.

This circuit is called a **half adder** and is suitable only for adding the
least significant bits (the rightmost bits) of two multi-bit operands. For
all other pairs of bits, there may be a carry-in from a preceding sum.

A
circuit that can add two digits plus the carry-in is called a **full adder**. In the table below,
the carry-in is Cin and the carry-out is C.

A full-adder can be constructed using 2 half-adders and an OR gate (see the circuit below). The first half adder adds the values of A and B. The second half-adder adds the resulting sum and the value of the carry in. There will be a carry out if either of these operations results in a carry. (If you think about it a while, you will discover that it is not possible for both of these operations to generate a carry at the same time.)